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Job Description
5+ years industry experience with below skillset :
Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodologyAssertion coding and converging on Formal toolsMust have worked on Jasper Gold or VC Formal toolsUnderstanding of common flows, such as Sequential equivalence checks, Register verification using formal is a plusExperience in dynamic verification methodologies will be a plusExperience with scripting languages such as Perl, Python is a plus
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