[CONTRACT] UVM Verification Engineer

Job Description

Job Title: UVM Verification Engineer
Job Type: Contract
Duration: 6-7 Month Initial with chance to renew
Location: Remote/Ireland
Start: ASAP

We currently require a an ASIC Verification Engineer on a contract basis to start ASAP with our client.

The successful engineer will contribute towards the design, integration and verification of new IP products for high speed communications.

For this, our client requires knowledge and experience in the following areas:
- Experience in both ASIC design and Verification
- Strong background in RTL design in Verilog
- Verification in SystemVerilog and UVM
- Knowledge of high speed interface and design such as SERDES, PCIe, USB, SATA etc.


For more information on the position and the company, please